The devolution of synchronizers

Synchronizers play a key role in multi-clock domain systems on chip. Traditionally, improvement of synchronization parameters with scaling has been assumed. In particular, the resolution time constant (τ) has been expected to scale proportionally to the gate delay ´FO4´. Recent measurements, however, have yielded counter-examples showing a degradation of τ with scaling. In this paper we present these findings and we show circuit analysis and simulations results, demonstrating the devolution of synchronization parameters. Measurements have been made on a 65nm circuit and on series of FPGA devices. The τ measured on the 65nm circuit was about 100ps, in contrast with expectations of less than 30ps. Three similar FPGA devices, fabricated in 130, 90 and 65nm processes, yielded values of 57, 51 and 73ps, respectively, showing a significant increase in 65nm relative to older generations. The analysis is validated by simulations that predict further increase of τ for future technologies.