IP-based design of custom field programmable network processors

A methodology was tested, based on reuse, to design ASIPs (application specific programmable processors) at ASIC cost. Criteria are defined to identify reusable semantics (noninstantiated intellectual properties) within functional specifications written in C. These are isolated as hierarchically nested, object oriented C++ behaviors. A “what-if” exploration flow brings to the optimized hw and sw sorting of every such IP inside an algorithm running on a programmable architecture. The specific architecture is modeled and taken into account by the sw and hw synthesis tools, not in the IP model. We evaluated the procedure developing a VLIW custom programmable processor, re-configurable on both hw and sw. This emulator is a prototype for fixed or programmable DSPs, and an archetype of a real-time field retargetable “class” processor, with optimum speed and power performance tuned to every new algorithm/data couple within a certain class of applications. An experiment on processing the real time code for multi-mode communication terminals is reported