An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications

An ultra-low power (ULP) SoC including an IEEE802.15.4 2.4 GHz transceiver designed in 130 nm CMOS technology is presented. Power consumption was minimized by using a concurrent system and design optimization to avoid the over-specification of blocks. A novel minimum complexity partial correlation algorithm is used in the digital baseband receiver and drains an average of 4802 A (packet PSDU=20 bytes). At 1.2 V, the transceiver drains 5.4 mW and 8.1 mW in RX and TX active modes, respectively, and achieves 1% PER for a -81 dBm input power. For a 250 kbit/s data rate, the transceiver attains an energy efficiency of 21.5 nJ/bit RX and 32.5 nJ/bit TX.