DocumentCode
3491880
Title
A 5-bit 1-GS/s Flash-ADC in 0.13-μm CMOS Using Active Interpolation
Author
Viitala, Olli ; Lindfors, Saska ; Halonen, Kari
Author_Institution
Electron. Circuit Design Lab., Helsinki Univ. of Technol.
fYear
2006
fDate
19-21 Sept. 2006
Firstpage
412
Lastpage
415
Abstract
This work presents a 5-bit 1-GS/s flash-ADC in 0.13-μm CMOS technology. An active interpolation topology is used in the comparator inputs to reduce power consumption and input capacitance of the converter. Operating at 1.056-GS/s the ADC consumes 46 mW of power from a 1.2 V supply and provides an ENOB of 4.73 bits and an SFDR of 43.2 dBc at a signal frequency of 102 MHz. The ADC has an ERBW of 470 MHz and a FoM of 1.8 pJ/convstep. Area consumption for the converter is 0.2 mm2.
Keywords
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); interpolation; power consumption; 0.13 micron; 1.2 V; 102 MHz; 4.73 bit; 46 mW; 470 MHz; 5 bit; CMOS; active interpolation topology; comparator inputs; converter input capacitance; converter power consumption; flash-ADC; Bandwidth; CMOS technology; Capacitance; Electronic circuits; Energy consumption; Frequency; Interpolation; Preamplifiers; Resistors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
Conference_Location
Montreux
ISSN
1930-8833
Print_ISBN
1-4244-0303-0
Type
conf
DOI
10.1109/ESSCIR.2006.307618
Filename
4099791
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