A multi-GOPS SIMD core for systematic signal processing

Author

Bonnot, Philippe ; Kajfasz, Philippe

Author_Institution

Thomson-CSF, Gennevilliers, France

Volume

2

fYear

1999

fDate

5-8 Sep 1999

Firstpage

953

Abstract

In many digital signal processing applications, the major computational load is spent on front-end processing. This front-end processing is mainly based on systematic loops that do not need general purpose DSPs. We describe in this paper a programmable signal processing IP (Intellectual Property) which offers the computation power of several DSP cores thanks to the opportunities of simplifications allowed by systematic processing. After a brief description of the aimed class of applications and the architecture of the processor core, the paper describes the programming tools developed for this IP. Those tools permit easy programming by taking advantage of the regularity of the tasks performed

Keywords

VLSI; digital signal processing chips; fixed point arithmetic; industrial property; parallel architectures; computation power; digital signal processing applications; front-end processing; intellectual property; multi-GOPS SIMD core; programmable signal processing IP; systematic loops; systematic processing; systematic signal processing; task regularity; Adaptive signal processing; Arithmetic; Digital signal processing; Digital signal processing chips; Flexible printed circuits; Integrated circuit interconnections; Intellectual property; Multidimensional signal processing; Signal processing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.813390

Filename

813390