A 211 GOPS/W dual-mode real-time object recognition processor with Network-on-Chip

Author

Kim, Kwanho ; Kim, Joo-Young ; Lee, Seungjin ; Kim, XMinsu ; Yoo, Hoi-Jun

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon

fYear

2008

fDate

15-19 Sept. 2008

Firstpage

462

Lastpage

465

Abstract

This paper presents a 211 GOPS/W real-time object recognition processor with network-on-chip (NoC). The chip integrates 8 linearly connected SIMD clusters with 8 4-way VLIW processing elements (PEs) per cluster. The SIMD/MIMD dual-mode object recognition processor exploits both data-level and object-level parallelism based on the NoC configuration. The 8-way SIMD PE cluster is optimized for data-intensive object recognition tasks. Packet-based power management scheme is employed for low power consumption. The proposed processor takes 36 mm² in 0.13 mum CMOS process and achieves a peak performance of 96 GOPS at 200 MHz with 392 mW power consumption.

Keywords

CMOS integrated circuits; VHF circuits; multiprocessing systems; network-on-chip; object recognition; parallel processing; real-time systems; CMOS process; VLIW processing elements; dual-mode processor; frequency 200 MHz; linearly connected SIMD clusters; low power consumption; network-on-chip; object recognition processor; object-level parallelism; packet-based power management; power 392 mW; real-time processor; size 0.13 mum; Circuits; Energy consumption; Energy management; Feature extraction; Image processing; Network-on-a-chip; Object recognition; Packet switching; Parallel processing; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European

Conference_Location

Edinburgh

ISSN

1930-8833

Print_ISBN

978-1-4244-2361-3

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2008.4681892

Filename

4681892