• DocumentCode
    3492105
  • Title

    A 24-Gb/s 27 - 1 Pseudo Random Bit Sequence Generator IC in 0.13 μm Bulk CMOS

  • Author

    Weiss, Franz ; Wohlmuth, Hans-Dieter ; Kehrer, Daniel ; Scholtz, Arpad L.

  • Author_Institution
    INFINEON AG, Neubiberg
  • fYear
    2006
  • fDate
    19-21 Sept. 2006
  • Firstpage
    468
  • Lastpage
    471
  • Abstract
    This work presents a 24Gb/s pseudo random bit sequence (PRBS) generator with a sequence length of 27 - 1. The circuit uses an interleaved linear feedback shift register and multiplexing architecture. An output voltage swing of 280mVpp is achieved for 24Gb/s data rate and 390mVpp for 10Gb/s. The circuit features a trigger output which allows to trigger the eye or the sequence pattern. The circuit is manufactured in 0.13 mum bulk CMOS technology and draws 183 mA at 1.5 V supply voltage
  • Keywords
    CMOS logic circuits; random number generation; shift registers; 0.13 micron; 1.5 V; 10 Gbit/s; 183 mA; 24 Gbit/s; 280 mV; 390 mV; CMOS; integrated circuit; interleaved linear feedback shift register; multiplexing architecture; pseudo random bit sequence generator; Bit rate; CMOS technology; Circuit testing; Data communication; Integrated circuit technology; Linear feedback shift registers; Multiplexing; Shift registers; System testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
  • Conference_Location
    Montreux
  • ISSN
    1930-8833
  • Print_ISBN
    1-4244-0303-0
  • Type

    conf

  • DOI
    10.1109/ESSCIR.2006.307482
  • Filename
    4099805
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3492105