Scan-path based testing of systems on a chip

An effective, low overhead cost method for isolating and testing cores and UDLs on a SOC. The added hardware for test application and compaction as part of the CUT when generating test patterns. These patterns where supplied to the CUT through the scan chain of the other components on the chip. The response to the test was also streamed out of the chip using some other sections of the scan chains. Compared to the use of register collar around the cores, our methodology yield lower hardware overhead area and comparable test length and fault coverage. The proposed approach is easily applicable to SOC using BIST