Property-based testability analysis for hierarchical RTL designs

We present an analysis methodology that identifies testability bottlenecks in RTL designs, based on the concept of transparency properties. We discuss a hierarchical test generation methodology, wherein test is locally generated for each module and subsequently translated into global design applicable test. We introduce the notion of transparency properties for capturing test translation related behavior of modules, without reasoning on the complete functionality of the design. A recursive search algorithm that combines properties into test justification and propagation paths and reveals the reachability bottlenecks for each module in the design is subsequently devised. An ATPG-based experimental setup validates that the proposed methodology identifies accurately the test translation bottlenecks in the hierarchical design