Title :
Path delay fault testing of Benes multistage interconnection networks
Author :
Vergos, H.T. ; Bellos, M. ; Nikolos, D.
Author_Institution :
Dept. of Comput. Eng. & Inf., Patras Univ., Greece
Abstract :
In this paper we present two methods for path delay fault testing of circuit-switched Benes Multistage Interconnection Networks (MINs) with centralized control. Although the number of paths is O(n3), the first method exploiting the inherent parallelism of the Benes MIN requires O(n2) pairs of test vectors. In the second method we propose the selection of a minimal subset of paths, that are robustly testable by only O(log2n) test vector pairs. The delay along all other paths can be calculated based on the selected path delays
Keywords :
VLSI; centralised control; circuit switching; delays; integrated circuit testing; logic testing; microprocessor chips; multistage interconnection networks; Benes multistage interconnection networks; VLSI chip testing; centralized control; circuit-switched Benes MIN; parallel testing; path delay fault testing; path selection based method; test vector pairs; Centralized control; Circuit faults; Circuit testing; Computer networks; Degradation; Delay effects; Joining processes; Multiprocessor interconnection networks; Propagation delay; Switches;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.813425