Design of a 1.8V 6-bit 100MSPS 5mW CMOS A/D Converter with Low Power Folding-Interpolation Techniques

Author

Hwang, Sanghoon ; Moon, Junho ; Jung, Seunghwi ; Song, Minkyu

Author_Institution

Dept. of Semicond. Sci., Dongguk Univ., Seoul

fYear

2006

fDate

Sept. 2006

Firstpage

548

Lastpage

551

Abstract

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm² in 0.18mum CMOS technology

Keywords

CMOS integrated circuits; analogue-digital conversion; interpolation; 0.18 micron; 1.8 V; 16 bit; 4.5 mW; 5 mW; 50 MHz; CMOS A/D converter; CMOS analog-to-digital converter; CMOS technology; effective resolution bandwidth; folding block number; folding type ADC; low power folding-interpolation techniques; resistive interpolation technique; Analog-digital conversion; CMOS technology; Circuit synthesis; Clocks; Energy consumption; Feedback amplifiers; Interpolation; Moon; Phased arrays; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European

Conference_Location

Montreux

ISSN

1930-8833

Print_ISBN

1-4244-0303-0

Type

conf

DOI

10.1109/ESSCIR.2006.307511

Filename

4099825