DocumentCode :
3492505
Title :
A 10-bit ENOB 50-MS/s Pipeline ADC in 130-nm CMOS at 1.2 V Supply
Author :
Treichler, Jürg ; Huang, Qiuting ; Burger, Thomas
Author_Institution :
Integrated Syst. Lab., ETH Zurich
fYear :
2006
fDate :
Sept. 2006
Firstpage :
552
Lastpage :
555
Abstract :
This paper describes the implementation of a 10-bit ENOB 50-MS/s CMOS pipeline analogue-to-digital converter (ADC) in a 130-nm process with a supply voltage of 1.2 volts and on-chip voltage buffers. The pipeline stages are scaled in current and area consumption to five different sizes, and OTAs with double regulation provide high gain in the first four stages. A differential difference comparator architecture reduces the amount of needed MiM-capacitors. The converter reaches a dynamic range of 11 bits, and the total power consumption of the core is 122 mW
Keywords :
CMOS integrated circuits; analogue-digital conversion; buffer circuits; comparators (circuits); operational amplifiers; 1.2 V; 10 bit; 11 bit; 122 mW; 130 nm; CMOS pipeline analogue-to-digital converter; MiM-capacitors; OTA; differential difference comparator architecture; on-chip voltage buffers; pipeline ADC; CMOS process; CMOS technology; Circuit noise; Digital signal processing; Dynamic range; Dynamic voltage scaling; Energy consumption; Pipelines; Switches; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
Conference_Location :
Montreux
ISSN :
1930-8833
Print_ISBN :
1-4244-0303-0
Type :
conf
DOI :
10.1109/ESSCIR.2006.307512
Filename :
4099826
Link To Document :
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