Comparison between bipolar and NMOS transistors in linearization technique at 5GHz low noise amplifier

Author

Galal, A.I.A. ; Pokharel, R.K. ; Kanaya, H. ; Yoshida, K.

Author_Institution

Grad. Sch. of Inf. Sci. & Electr. Eng., Kyushu Univ., Fukuoka

fYear

2008

fDate

16-20 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

This paper presents a comparison between bipolar and NMOS transistor to get high linearity amplifier. Using bipolar transistor, the amplifier has high linearity, and it does not sensitive to component variations. High linear amplifier using bipolar transistor has been designed and was fabricated using TSMC 0.18 um CMOS 1P6M process. The high linearity amplifier exhibits measurements results as 10.5 dB gain, noise figure less than 2.1 dB, input return loss is less than -15.9 dB, output return loss less than -15.8 dB, input third order intercept point is more than 16 dBm, and 7.6 mW of power consumption at 5 GHz.

Keywords

CMOS integrated circuits; MOSFET; bipolar transistors; linearisation techniques; low noise amplifiers; CMOS 1P6M process; NMOS transistors; TSMC; bipolar transistors; frequency 5 GHz; gain 10.5 dB; high linearity amplifier; linearization technique; low noise amplifier; noise figure; power 7.6 mW; power consumption; Bipolar transistors; CMOS process; Gain measurement; High power amplifiers; Linearity; Linearization techniques; Loss measurement; Low-noise amplifiers; MOSFETs; Power measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2008. APMC 2008. Asia-Pacific

Conference_Location

Macau

Print_ISBN

978-1-4244-2641-6

Electronic_ISBN

978-1-4244-2642-3

Type

conf

DOI

10.1109/APMC.2008.4958637

Filename

4958637