Development of on-chip double-shielded quantum Hall device for use in ac quantized Hall resistance measurement

Author

Oe, T. ; Matsuhiro, K. ; Domae, A. ; Urano, C. ; Fujino, H. ; Ishii, H. ; Itatani, T. ; Sucheta, G. ; Maezawa, M. ; Kiryu, S. ; Kaneko, N.

Author_Institution

Nat. Metrol. Inst. of Japan (NMIJ), Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan

fYear

2010

fDate

13-18 June 2010

Firstpage

376

Lastpage

377

Abstract

We have developed a on-chip double-shielded quantum Hall device and a double-shielded chip-carrier. The device in conjunction with the carrier will realize impedance standard based on the quantum Hall effect. In this configuration, the Hall bar is covered by separated on-chip shields and shields of the chip carrier to retrieve the leakage current. In this paper, we show detail of the QHR device fabrication and the structure of the chip carrier.

Keywords

Hall effect devices; electric resistance measurement; integrated circuit packaging; leakage currents; quantum Hall effect; shielding; AC quantized Hall resistance measurement; Hall bar; QHR device fabrication; double-shielded chip-carrier; impedance standard; leakage current; on-chip double-shielded quantum Hall device; quantum Hall effect; Ceramics; Connectors; Electrical resistance measurement; Electromagnetic measurements; Electronics industry; Fabrication; Gallium arsenide; Gold; Industrial electronics; Metrology;

fLanguage

English

Publisher

ieee

Conference_Titel

Precision Electromagnetic Measurements (CPEM), 2010 Conference on

Conference_Location

Daejeon

Print_ISBN

978-1-4244-6795-2

Type

conf

DOI

10.1109/CPEM.2010.5545329

Filename

5545329