Title :
New Floating Gate Self-Aligning Technology for Multilevel NOR Flash Memory
Author :
Lee, Wook H. ; Kim, Jae-Hoon ; Byun, Ki-Yeol ; Lee, Bong-Yong ; Sim, Sang-Pil ; Park, Chan-Kwang ; Kim, Kinam
Author_Institution :
Memory Div., Samsung Electron.
Abstract :
This paper describes the key technology to realize a scaled multilevel NOR flash memory with an improved gate oxide integrity. It is found that a thin poly-Si employed in STI formation is a good buffer layer to prevent the oxide local thinning at STI corners of both cell and peripheral areas. Using the poly-Si as a sacrificial-layer during tunnel oxide growth, a 65nm NOR flash memory with a cell size of 0.039 mum2 has been developed and achieved the multilevel cell (MLC) operation. Also, an improved post-cycled retention characteristics has been obtained
Keywords :
NOR circuits; buffer layers; field effect logic circuits; flash memories; semiconductor growth; 65 nm; buffer layer; floating gate technology; improved gate oxide; multilevel NOR flash memory; multilevel cell operation; post-cycled retention; self-aligning technology; thin poly-Si; tunnel oxide growth; Buffer layers; Cobalt; Flash memory; Interference; Lithography; Nonvolatile memory; Oxidation; Paper technology; Silicides; Threshold voltage;
Conference_Titel :
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0301-4
DOI :
10.1109/ESSDER.2006.307677
