An efficient architecture for high speed turbo decoders

Turbo codes not only achieve near Shannon-capacity performance, but also have decoders with modest complexity, which is crucial for implementation. So far efficient architectures for decoding of turbo codes have been proposed that are suitable for sequential processing. In this paper a novel parallel processing architecture for a very high-speed turbo decoder is presented. The performance of this decoder and the tradeoff between speed and efficiency are discussed. It is shown that some decoders can run faster by some orders of magnitude while maintaining almost the same processing load. A systolic implementation of this decoder is presented at the end.