Design of an IPv4/IPv6 Translator Based on SOPC Technology

Author

Liu, Wai-xi ; Tang, Run-hua ; Li, Hui ; Hu, Xiao

Author_Institution

Guangzhou Univ., Guangzhou

fYear

2008

fDate

6-8 April 2008

Firstpage

786

Lastpage

790

Abstract

As the key device of IPv4-IPv6 interconnection, an IPv4/IPv6 translator has to support high forward speed. However, there is no existing solution published to satisfy the requirement. In this paper, a solution of IPv4/IPv6 translator based on SOPC (system on programmable chip) technology is proposed. It is based on top-down design methodology. In the development process, VHDL programming and schematic design are both used and the system is implemented on one FPGA chip. Test results show that its maximum forward speed is 800 Mbps and its delay time is 40 ns from v4 to v6 network, and 96 ns from IPv6 to IPv4.

Keywords

IP networks; field programmable gate arrays; hardware description languages; integrated circuit design; protocols; system-on-chip; FPGA chip; IPv4/IPv6 translator; VHDL programming; schematic design; system on programmable chip; Application specific integrated circuits; Delay effects; Design methodology; Embedded system; Field programmable gate arrays; Linux; Next generation networking; Protocols; Testing; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Networking, Sensing and Control, 2008. ICNSC 2008. IEEE International Conference on

Conference_Location

Sanya

Print_ISBN

978-1-4244-1685-1

Electronic_ISBN

978-1-4244-1686-8

Type

conf

DOI

10.1109/ICNSC.2008.4525322

Filename

4525322