Title :
LASER Anneal to Enable Ultimate CMOS Scaling with PMOS Band Edge Metal Gate/High-K Stacks
Author :
Gilmer, D.C. ; Schaeffer, J.K. ; Taylor, W.J. ; Spencer, G. ; Triyoso, D.H. ; Raymond, M. ; Roan, D. ; Smith, J. ; Capasso, C. ; Hegde, R.I. ; Samavedam, S.B.
Author_Institution :
Austin Silicon Technol. Solutions, Freescale Semicond. Inc., Austin, TX
Abstract :
For the first time, we report on the beneficial result for minimizing the activation thermal budget using LASER anneals with metal-oxide-gate-electrode/high-k dielectric MOSFETs. With LASER activation, EOT for PMOS conductive metal-oxide gated devices is reduced 4-5Aring compared to conventional RTP activation methods leading to more aggressive ultimate CMOS scaling when using a conductive metal-oxide for the PMOS gate electrode
Keywords :
CMOS integrated circuits; MOSFET; dielectric devices; laser beam annealing; rapid thermal annealing; 4 to 5 Aring; CMOS scaling; LASER activation; LASER anneal; PMOS band edge metal gate; PMOS conductive metal-oxide gated devices; PMOS gate electrode; RTP activation methods; activation thermal budget; high-k dielectric MOSFET; high-k stacks; metal-oxide-gate-electrode MOSFET; Conducting materials; Dielectric materials; Electrodes; High K dielectric materials; High-K gate dielectrics; MOSFETs; Rapid thermal annealing; Semiconductor lasers; Silicon; Temperature;
Conference_Titel :
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0301-4
DOI :
10.1109/ESSDER.2006.307710
