High voltage power MOSFET with reduced JFET area design

A high voltage power vertical double-diffused MOSFET with reduced JFET area by using an overall implantation was discussed. The reduced JFET area realizes a low gate charge and a high switching speed, due to the reduction of the gate-drain overlapped area. The measured gate-drain charge and gate charge can be improved by 61.1% and 71.8 %, respectively. The F.O.M of the proposed device and the conventional one is 64.4 nΩ×C and 190.9 nΩ×C, respectively. We also discussed the reliability issue and compared the avalanche capability to the proposed structure and the conventional device. The ruggedness of the proposed devices can be improved by a higher cell density design with a planar oxide self align p⁺ implantation process.