Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study

Author

Brown, Andrew R. ; Roy, Gareth ; Asenov, Asen

Author_Institution

Dept. of Electron. & Electr. Eng., Glasgow Univ.

fYear

2006

fDate

19-21 Sept. 2006

Firstpage

451

Lastpage

454

Abstract

In this paper we present a 3D simulation study of the effect of Fermi level pinning along polysilicon gate grain boundaries on nano-MOSFET variability. Pinning of the Fermi level results in variations between devices depending on the random pattern of grain boundaries within the gate. We present a coherent 3D simulation methodology demonstrating the necessity of statistical simulations. As an illustration of our approach, we have carried out a statistical analysis of the variation in threshold voltage induced by polysilicon grain boundaries for a 30 nm MOSFET

Keywords

Fermi level; MOSFET; grain boundaries; semiconductor device models; statistical analysis; 30 nm; Fermi level pinning; nanoMOSFET variability; polysilicon gate grain boundaries; statistical analysis; statistical simulations; threshold voltage; Circuits and systems; Doping; Fluctuations; Grain boundaries; MOSFET circuits; Nanoscale devices; Photonic band gap; Silicon; Statistical analysis; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Conference_Location

Montreux

ISSN

1930-8876

Print_ISBN

1-4244-0301-4

Type

conf

DOI

10.1109/ESSDER.2006.307735

Filename

4099953