Wire-Sizing for Interconnect Performance Optimization Considering High Inductance Effects

In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first present an equivalent Elmore delay metric for distributed parameter interconnect lines considering high inductance effects based on the two-pole approximation model, and then propose a simplified near-optimal uniform wire-sizing scheme. Based on the closed form delay metric, a delay-area tradeoff is proposed to interconnect optimizations, and the delay metric can be applied to other optimization problems in a similar way. Experimental results show that the method we proposed is of great accuracy and efficiency, and will be very useful for better design convergence and simpler routing architectures.