Evaluating location of memory controller in on-chip communication networks

Rapid increasing in the number of cores in a chip demands more memory bandwidth. Memory request pass hops to reach memory controllers. Therefore, memory controllers can be one of the main sources of contention on the chip. In this paper, first, we demonstrate that fewer channels load in the network does not always imply less average latency, thus, we consider a hierarchical approach in placing memory controllers to reduce latency by 20%. Second, we illustrate how by increasing the number of memory controllers the average latency and energy consumption can be significantly reduced. In addition, it is shown how for a constant number of memory controllers, their appropriate placement and suitable routing algorithms can reduce the latency. We further discuss the correlation between location of memory controllers and routing algorithms, and propose a heuristic algorithm for placement of memory controllers to reduce their space exploration.