Measuring Leakage Power in Nanometer CMOS 6T-SRAM Cells

Digital systems design has traditionally taken into account dynamic power as a measure of energy consumption efficiency. However, in current and emerging generations of digital circuits leakage power is becoming to total energy consumption as important as dynamic power. More portable electronic devices are available everyday. Such devices are using newer semiconductor technologies that allow to fit more transistors per square millimeter. This increase in transistors density produces increases in power and temperature densities. Increases in transistors´ temperature exponentially impact the leakage power. For this reason, it is important to consider leakage power consumption in the design of digital systems. In this work we develop the design of a 6T-SRAM cell utilizing two semiconductor technologies and a range of circuit design parameters. We estimate the leakage power for each of the designs. Results among our designs are compared in order to observe leakage trends within the studied technologies and parameters to provide design guidelines for leakage power-aware digital systems