Secure AES Coprocessor Against Power Analysis for Wireless Sensor Networks

Cryptographic coprocessors for wireless sensor nodes are resource-constrained devices, which require low power and a small size. Besides, with the advent of side channel attacks, resistance to such attacks becomes another major requirement. This paper describes a low-cost and high-security Advanced Encryption Standard (AES) coprocessor implementation and an optimization scheme for Wireless Sensor Networks (WSN) systems. The compact architecture of AES is applied to optimize the size of AES circuits. Its impact on the security against power analysis attack is analyzed, which is important for many WSN applications. A novel method, using inhomogeneous S-Boxes instead of fixed S-Boxes, is proposed to resist power analysis attacks. The AES coprocessor was implemented with UMC 0.25 mum 1.8v CMOS standard cell library and power analysis experiments were conducted. The results demonstrate that our proposed design has very low hardware cost and enhances the AES secure characteristics effectually.