EMC modeling and simulation on chiplevel

Author

Steinecke, T. ; John, W. ; Koehne, H. ; Schmidt, M.

Author_Institution

Infineon Technol. AG, Munich, Germany

Volume

2

fYear

2001

fDate

2001

Firstpage

1191

Abstract

Due to increasing demands for reduced electromagnetic emission on chip-level in combination with more complex circuits and faster design cycles, it is mandatory to spend effort on EMC models and simulation for chip design. In this paper, a three-level approach, based on: (1) testchip design and measurement; (2) RLC-extraction of supply system plus transistor netlist simulation; and (3) behavioural models for simple gates and complex digital modules are presented. Correlation between results of those three levels has to be established, and finally behavioural models for complete CMOS VLSI chips have to be derived and implemented in a simulation environment

Keywords

CMOS integrated circuits; VLSI; electromagnetic compatibility; electromagnetic interference; integrated circuit modelling; CMOS VLSI chips; RLC-extraction; behavioural models; chip design; chip-level EMC modelling; chip-level EMC simulation; complex circuits; complex digital modules; design cycles; electromagnetic emission reduction; gates; netlist simulation; simulation environment; test chip design; test chip measurement; Chip scale packaging; Circuit simulation; Circuit testing; Electromagnetic compatibility; Electromagnetic measurements; Electromagnetic modeling; Semiconductor device measurement; Semiconductor device modeling; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility, 2001. EMC. 2001 IEEE International Symposium on

Conference_Location

Montreal, Que.

Print_ISBN

0-7803-6569-0

Type

conf

DOI

10.1109/ISEMC.2001.950600

Filename

950600