Title :
Design Space Exploration for an Adaptive Noise Cancellation Algorithm
Author :
de Icaya, E.M. ; Rodellar, V. ; González, C. ; Peinado, V. ; García, V.
Author_Institution :
Dept. ATC, Escuela Universitaria de Informatica
Abstract :
The most difficult aspect of system-level design consists in make a good selection between the multiplicities of options in the task level specification. This process relies heavily on the quality of the area, execution time and power consumption measures; the usefulness of the generated partition depends on how accurate these estimation measures are. The aim of this paper is to probe a general sequence of actions to obtain these values. The approximation has consisted of the specification of the problem in ANSI C and its transformation into assembler code for several DSP platforms and into RTL VHDL synthesizable code as input to automatic synthesis tools. The outputs of the estimates measures obtained when the sequence of actions is completed feed the partitioning phase. Also, the assembler and RTL VHDL code chosen may be reused in the cosynthesis stage. A noise canceller filter as example of application is presented
Keywords :
C language; digital signal processing chips; formal specification; hardware description languages; hardware-software codesign; logic partitioning; program assemblers; ANSI C; DSP platforms; RTL VHDL synthesizable code; adaptive noise cancellation algorithm; assembler code; automatic synthesis tools; design space exploration; noise canceller filter; power consumption measures; system-level design; Algorithm design and analysis; Area measurement; Assembly; Energy consumption; Noise cancellation; Partitioning algorithms; Power measurement; Space exploration; System-level design; Time measurement;
Conference_Titel :
Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. IEEE International Conference on
Conference_Location :
San Luis Potosi
Print_ISBN :
1-4244-0690-0
Electronic_ISBN :
1-4244-0690-0
DOI :
10.1109/RECONF.2006.307769