Datapath and ISA Customization for Soft VLIW Processors

In this paper we examine the performance and area trade-offs resulting from customizing the datapath and instruction set architecture of a soft VLIW processor. In addition to describing the datapath and instruction set architecture of our processor, we describe a number of microarchitectural optimizations we used to reduce the area of the datapath. We also describe the tools we developed and used to customize, generate, implement, and program the processor. Our experimental results show that datapath and instruction set customization achieve high levels of performance, and that microarchitectural optimizations like selective data forwarding help keep FPGA resource utilization in check