Comparing NoC architectures for neural networks

Implementation of reconfigurable neural networks in hardware requires highly flexible connectivity, creating major architectural challenge. We perform an analytical evaluation and comparison of different configurable interconnect architectures (mesh NoC, tree, shared bus and point-to-point) emulating variants of two neural network topologies (having full and random exponential configurable connectivity). We derive analytical expressions and asymptotic limits for performance (in terms of bandwidth) and cost (in terms of area and power) of the interconnect architectures considering three communication methods (unicast, multicast and broadcast). It is shown that planar structure, fault and drop tolerance and pulse-information encoding in spiking neural networks makes simple multicast mesh network-on-chip suitable for massively parallel communication required by these networks. Simulation results successfully validate the analytical models and the asymptotic behavior of the network as a function of its size.