Sub-threshold and near-threshold SRAM design

Voltage scaling is one of the most effective techniques for power reduction in digital VLSI design, however various challenges arise when operating standard SRAM circuits at low voltages. These include loss of static noise margins, extreme fluctuations in device currents under process variations and limitations on the number of cells connected to a single bitline. In this paper, we describe the challenges that arise while operating standard SRAM cells at low supply voltages and review several novel bitcells that have been presented in recent years to deal with these challenges.