Parallel instruction set extension identification

Modern embedded processors are often customized to accelerate native code. However, the design space exploration of hardware/software trade-offs is often time-intensive. To explore the design space of a processor´s instruction set, simulations are utilized. Instruction set extension identification is usually performed by analyzing the basic blocks of an application in a linear fashion. We present an instruction set extension identification pass implemented in the COINS compiler which can simultaneously enumerate candidate instruction set extensions in multiple basic blocks. Using benchmarks such as FFT and Dijkstra we show a compiler execution improvement of time up to 53.7% compared to the traditional sequential approach.