Design and analysis of 3D IC-based low power stereo matching processors

Author

Seung-Ho Ok ; Kyeong-ryeol Bae ; Sung Kyu Lim ; Byungin Moon

Author_Institution

Sch. of Electron. Eng., Kyungpook Nat. Univ., Daegu, South Korea

fYear

2013

fDate

4-6 Sept. 2013

Firstpage

15

Lastpage

20

Abstract

This paper presents comprehensive design and analysis results of 3D IC-based low-power stereo matching processors. Our design efforts range from architecture design and verification to RTL-to-GDSII design and sign-off analysis based on GlobalFoundries 130-nm PDK. We conduct comprehensive studies on the area, performance, and power benefits of our 3D IC designs over 2D IC designs. Our 2-tier 3D IC designs attain 43% area, 14% wire length, and 13% power saving over 2D IC designs. We also study a pipeline-based partitioning method shown to be effective at minimizing power consumption and the total number of TSVs while balancing the size of each tier.

Keywords

digital signal processing chips; integrated circuit design; low-power electronics; stereo image processing; three-dimensional integrated circuits; 2D IC designs; 3D integrated circuits; RTL-to-GDSII design; TSV; architecture design; low power stereo matching processors; pipeline-based partitioning method; sign-off analysis; size 130 nm; through-silicon-via; Clocks; Integrated circuits; Pipeline processing; Program processors; Random access memory; Three-dimensional displays; Wires; 3D IC; Stereo matching processor; TSV; low-power design;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on

Conference_Location

Beijing

Print_ISBN

978-1-4799-1234-6

Type

conf

DOI

10.1109/ISLPED.2013.6629260

Filename

6629260