SRAM cell optimization for low AVT transistors

In this paper, we describe a six-transistor static random access memory (SRAM) cell optimization methodology for transistors with significantly improved matching, while maintaining compatibility with the baseline design. We briefly describe the reduced AV_T transistors and show that they allow substantially improved minimum SRAM operating voltage (V_min) and improved array leakage. Using an efficient design of experiments (DOE) factorial as a pseudo-Monte Carlo generator, points on the tail of the distribution are directly simulated. The highly efficient method is shown to allow optimization and `what if´ scenario investigations. Simulation and silicon results on a 65-nm process as well as simulation results on a 28-nm process are shown.