DocumentCode :
3496970
Title :
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches
Author :
Sharad, Mrigank ; Venkatesan, R. ; Raghunathan, Anand ; Roy, Kaushik
fYear :
2013
fDate :
4-6 Sept. 2013
Firstpage :
64
Lastpage :
69
Abstract :
Spin-based devices promise to revolutionize computing platforms by enabling high-density, low-leakage memories. However, stringent tradeoffs between critical design metrics such as read and write stability, reliability, density, performance and energy-efficiency limit the efficiency of conventional spin-transfer-torque devices and bit-cells. We propose a new multi-level cell design with domain wall magnets (DWM-MLC) that significantly improves upon the read/write performance, density, and write energy consumption of conventional spin memories. The fundamental design tradeoff between read and write operations are addressed in DWM-MLC by decoupling the read and write paths, thereby allowing separate optimization for reads and writes. A thicker tunneling oxide is used for higher readability, while a domain-wall-shift (DWS) based write mechanism is used to improve write speed and energy. The storage of multiple bits per cell and the ability to use smaller transistors lead to a net improvement in density compared to conventional spin memories. We perform a systematic evaluation of DWM-MLC at different levels of design abstraction. At the circuit level, DWM-MLC achieves 2X improvement in density, read energy and read latency over its 1-bit counterpart. We evaluate an “all-spin” cache hierarchy that uses DWM-MLC for both L1 and L2, resulting in 4.4X (1.7X) area improvement and 10X (2X) energy reduction at iso-performance over SRAM (STT-MRAM).
Keywords :
MRAM devices; SRAM chips; cache storage; magnetic domain walls; spin polarised transport; DWM-MLC; DWS; SRAM; STT-MRAM; all-spin cache hierarchy; critical design metrics; design abstraction; domain wall magnets; domain wall shift; energy efficiency; multilevel cell design; multilevel magnetic RAM; read energy; read latency; read-write performance; spin memories; spin-based devices; spin-transfer-torque devices; Decision support systems; Educational institutions; Electronic mail; Low-power electronics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4799-1234-6
Type :
conf
DOI :
10.1109/ISLPED.2013.6629268
Filename :
6629268
Link To Document :
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