DocumentCode
3497115
Title
A new interleaved three-level inverter
Author
Yisheng, Yuan
Author_Institution
East China Jiaotong Univ., Nanchang, China
fYear
2010
fDate
16-18 June 2010
Firstpage
232
Lastpage
235
Abstract
A new interleaved three-level inverter with reduced ripple current of filter inductor is proposed. This inverter consists of six power switches, including two interleaved power switches at the top location and the bottom location separately, and two double frequency power switches at the middle locations. The inverter theory and PWM method are explained. The ripple current expression equations of the proposed inverter and other two half-bridge inverter are derived and compared. A two-loop control strategy with disturbance forward suppression loop is proposed and adopted. A prototype verified the proposed inverter.
Keywords
Equations; Filtering theory; Inductors; Inverters; Logic gates; Switching frequency; Voltage control; Control strategy; Interleaved technique; Inverter; Three-level;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics for Distributed Generation Systems (PEDG), 2010 2nd IEEE International Symposium on
Conference_Location
Hefei, China
Print_ISBN
978-1-4244-5669-7
Type
conf
DOI
10.1109/PEDG.2010.5545900
Filename
5545900
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