Bipolar and CMOS low voltage-supply reduced-power voltage followers

Author

Ferri, Giuseppe ; Alfonsetti, Franco ; Cardarilli, Gian-Carlo ; Re, Marco

Author_Institution

Dipt. di Ingegneria Elettrica, l´´Aquila Univ., Italy

Volume

3

fYear

1999

fDate

1999

Firstpage

1503

Abstract

In this paper, we present a novel voltage follower topology, developed both in bipolar and in CMOS standard technologies. The buffers works at low supply voltages (±1 V for bipolar and ±0.75 V for CMOS) and have improved performance in terms of rail-to-rail input and output characteristics and low quiescent power consumption. The slew rate is very high if compared with other solutions presented in the literature. The determination of the efficiency factor, defined as GBW(MHz)*C_load(pF)/Power(mW), shows that our solutions are much better than the other topologies proposed in the literature

Keywords

CMOS analogue integrated circuits; bipolar analogue integrated circuits; low-power electronics; -0.75 V; -1 V; 0.75 V; 1 V; CMOS voltage followers; bipolar voltage followers; efficiency factor; low quiescent power consumption; low voltage supply; rail-to-rail input characteristics; rail-to-rail output characteristics; reduced-power voltage followers; slew rate; voltage follower topology; CMOS technology; Circuit topology; Current supplies; Energy consumption; Low voltage; Mirrors; Operational amplifiers; Rail to rail inputs; Rail to rail outputs; Standards development;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.814455

Filename

814455