DocumentCode :
349723
Title :
Offset- and gain-compensated track-and-hold stages
Author :
Huang, Yunteng ; Temes, Gabor C. ; Ferguson, Paul E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
Volume :
2
fYear :
1998
fDate :
1998
Firstpage :
13
Abstract :
A class of new fully-differential track-and-hold stages is presented. The gain of the stages does not depend on capacitor matching, and a predictive correlated-double-sampling scheme is used to reduce the effects of op-amp offset and finite dc gain. A prototype chip was fabricated in a 1.2 μm double-poly double-metal CMOS process. Measured results indicated that the proposed track-and-hold stage is superior in both speed and accuracy to other commonly used CMOS sample-and-hold stages implemented on the same chip
Keywords :
CMOS analogue integrated circuits; correlation methods; sample and hold circuits; signal sampling; 1.2 micron; accuracy; double-poly double-metal CMOS process; finite dc gain; fully-differential circuits; gain-compensated track-and-hold stages; op-amp offset; predictive correlated-double-sampling scheme; speed; Capacitors; Circuits; Clocks; Design engineering; Frequency; Operational amplifiers; Prototypes; Sampling methods; Switches; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
Type :
conf
DOI :
10.1109/ICECS.1998.814810
Filename :
814810
Link To Document :
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