• DocumentCode
    3497230
  • Title

    Beyond charge based computation: Design space exploration of spin transfer torque based MRAMs for embedded applications

  • Author

    Raychowdhury, Arijit

  • Author_Institution
    Georgia Institute of Technology, GA, USA
  • fYear
    2013
  • fDate
    4-6 Sept. 2013
  • Firstpage
    135
  • Lastpage
    138
  • Abstract
    Ever larger on-die memory arrays for future processors in CMOS logic technology drives the need for dense and scalable embedded memory alternatives beyond SRAM and eDRAM. Recent advances in non-volatile STT-RAM technology, which stores data by the spin orientation of a soft ferromagnetic material and shows current induced switching, have created interest for its use as embedded memory [1–3]. When a spin-polarized current passes through a mono-domain ferromagnet, it attempts to polarize the current in its preferred direction of magnetic moment. As the ferromagnet absorbs some of the angular momentum of the electrons, it creates a torque that causes a flip in the direction of magnetization in the ferromagnet. This is used in magnetic tunneling junction (MTJ) based spin torque transfer (STT) RAM cells where a thin insulator (MgO) is sandwiched between a fixed ferromagnetic layer (polarizer) and the free layer (storage node). This can be integrated in the metal stack (Fig. 1) and hence provide high memory density. Depending on the direction of the current flow (perpendicular to these layers in our study), the magnetization of the free layer is switched to a parallel (P: low resistance state) or anti-parallel (AP: high resistance state) state. The minimum size cell (mincell) contains an access transistor (Tx) of width 2F (WTX=2F, F: half-pitch of the process node) and a planar storage node of dimensions 2FxF. The area of the mincell is 3Fx2F=6F2. In this paper, we examine the design space for key magnetic material properties and access transistor needed for embedded on-die memory with adequate scalability, density, read/write performance and robustness against various intrinsic variabilities and disturbances. New models and simulation methodologies, calibrated to existing measurements [1], for read, write and disturbance mechanisms are developed. Different storage node structures and materials are evaluated to reveal the mos- promising scaling options.
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4799-1234-6
  • Type

    conf

  • DOI
    10.1109/ISLPED.2013.6629281
  • Filename
    6629281