Title :
Design of a low power 54×54-bit multiplier based on a pass-transistor logic
Author_Institution :
Dept. of Semicond. Sci., Dongguk Univ., Seoul, South Korea
Abstract :
In this paper, a pass-transistor logic with an efficient level restoration circuit is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of the proposed pass-transistor logic, a 54×54-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13.5 ns in a 0.6 μm single-poly triple-metal 3.3 V CMOS process
Keywords :
CMOS logic circuits; circuit feedback; delays; digital arithmetic; integrated circuit design; logic design; low-power electronics; multiplying circuits; 0.6 micron; 13.5 ns; 54 bit; conditional sum adder; high compression-rate compressors; level restoration circuit; low power multiplier; pMOS switches; pass-transistor logic; power consumption reduction; power optimization; propagation delay reduction; regenerative feedback; separated carry generation block; single-poly triple-metal CMOS process; speed optimization; Adders; CMOS logic circuits; Compressors; Encoding; Energy consumption; Feedback; Logic circuits; Logic design; Propagation delay; Switches;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.814821
