Title :
A repeater timing model and insertion algorithm to reduce delay in RC tree structures
Author :
Adler, Victor ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
Abstract :
One method of overcoming wire delay due to long resistive interconnect is to insert repeaters in the line. Analytical expressions describing a CMOS inverter driving an RC load have been integrated into a methodology for inserting repeaters in RC trees. These expressions are based on a short channel I-V model and exhibit less than 10% error. This repeater insertion methodology and its software implementation are described in this paper
Keywords :
CMOS digital integrated circuits; RC circuits; VLSI; circuit CAD; delay estimation; integrated circuit design; logic CAD; timing; CMOS inverter; RC load; RC tree structures; delay reduction; long resistive interconnect; repeater insertion algorithm; repeater timing model; short channel I-V model; wire delay; Analytical models; CMOS technology; Integrated circuit interconnections; Propagation delay; Repeaters; Semiconductor device modeling; Timing; Tree data structures; Very large scale integration; Wire;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.814827
