Title :
A configurable zero stall pipelined image processor architecture for FPGAs
Author_Institution :
Dept. of Comput. Sci., Coll. of Manage., Israel
Abstract :
Today´s FPGAs are capable of performing complex Image Processing schemes. In this paper we introduce a Configurable Zero Stall Image-Processing Pipelined Architecture. We define the handshake and discuss limitation resulting from configurability and complexity. We then present our solution for these issues allowing a simple yet effective circuit where no delay is introduced even though the output and the input of each Processing Element are isolated through a Moore state machine.
Keywords :
digital signal processing chips; field programmable gate arrays; image processing; pipeline processing; FPGA; Moore state machine; configurable zero stall pipelined image processor architecture; effective circuit; handshake; zero stall image-processing pipelined architecture; Clocks; Delay; Field programmable gate arrays; IP networks; Image processing; Pipelines; Registers; configurable image processor; image processor; pipelined image processor; zero stall;
Conference_Titel :
Electrical and Electronics Engineers in Israel (IEEEI), 2010 IEEE 26th Convention of
Conference_Location :
Eliat
Print_ISBN :
978-1-4244-8681-6
DOI :
10.1109/EEEI.2010.5662193
