Minimum supply voltage for sequential logic circuits in a 22nm technology

The minimum supply voltage (V_min) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and hold time. As supply voltage (V_cc) scales, statistical circuit simulations demonstrate that hold time increases faster than circuit delay or cycle time, consequently the required number of min-delay buffers increases. For this reason, a new hold-time violation metric defines V_min as the V_cc in which the hold time exceeds a target percentage of the cycle time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention V_min of 0.61Vnorm and a hold-time V_min of 0.73Vnorm, where V_norm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the hold-time V_min by 18% and the overall V_min by 16%.