Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor

Author

Drake, Alan J. ; Floyd, M.S. ; Willaman, Richard L. ; Hathaway, Derek J. ; Hernandez, Jaime ; Soja, Crystal ; Tiner, Marshall D. ; Carpenter, Gary D. ; Senger, Robert M.

Author_Institution

IBM Res., Austin, TX, USA

fYear

2013

fDate

4-6 Sept. 2013

Firstpage

193

Lastpage

198

Abstract

A 32nm SOI critical path monitor (CPM) that can provide timing measurements to a Digital PLL for dynamic frequency adjustments in the 8-core POWER7+™ microprocessor is described. The CPM calibrates to within 2% of cycle time from nominal to turbo voltages. Its voltage sensitivity is 10mV/bit. It tracks processor temperature sensitivity to within 1.5% of nominal frequency, and has a sample jitter less than 1.5% of nominal frequency. The ability to detect noise dynamically allows the system to operate the processor closer to its optimal frequency for any given voltage, resulting in lower voltage for power savings or higher frequency for performance improvements.

Keywords

elemental semiconductors; microprocessor chips; silicon-on-insulator; 8-core POWER7+ microprocessor; SOI CPM; SOI critical path monitor; digital PLL; dynamic frequency adjustment; dynamic noise detection; nominal frequency; nominal voltage; power savings; processor temperature sensitivity; single-cycle pulse-shaped critical path monitor; timing measurement; turbo voltage; voltage sensitivity; Calibration; Delays; Detectors; Image edge detection; Latches; Wires; Critical Path Monitor; DVFS; calibration; process variation;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on

Conference_Location

Beijing

Print_ISBN

978-1-4799-1234-6

Type

conf

DOI

10.1109/ISLPED.2013.6629293

Filename

6629293