Design and FPGA implementation of digit-serial FIR filters

Author

Valls, Javier ; Peiró, Marcos M. ; Sansaloni, Trini ; Boemo, Eduardo

Author_Institution

Dept. de Ingenieria Electron., Univ. Politecnica de Valencia, Spain

Volume

2

fYear

1998

fDate

1998

Firstpage

191

Abstract

In this paper the design of a family of digit-serial 8th-order FIR filters with programmable coefficients is presented. Both input data and coefficient size are 8 bits, but every filter of the family allows the computation with full precision of the intermediate data. The output data is truncated to 8 bits. The design of both, the digit-serial multiple precision multiply-and-accumulate and the digit-serial multiple-to-single precision converter, is detailed. All filters were implemented using an ALTERA FPGA being useful in applications with sample rate range from 5 to 22 MHz

Keywords

FIR filters; digital filters; field programmable gate arrays; logic design; programmable filters; 5 to 22 MHz; 8 bit; 8th-order FIR filters; ALTERA FPGA; FPGA implementation; digit-serial FIR filters; digit-serial multiple precision MAC; multiple-to-single precision converter; multiply/accumulate convertor; programmable coefficients; Adders; Artificial intelligence; Bismuth; Circuits; Clocks; Computer architecture; Costs; Digital signal processing; Field programmable gate arrays; Finite impulse response filter;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.814860

Filename

814860