DocumentCode
349757
Title
A design for test technique to increase the resolution of analogue supply current tests
Author
Chalk, C.D. ; Zwolinski, M.
Author_Institution
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
Volume
2
fYear
1998
fDate
1998
Firstpage
221
Abstract
By employing the new DFT technique proposed here, the fault coverage of the AC RMS supply current test for an opamp within a CMOS analogue multiplier circuit was increased to 100%. The DFTT scheme is based on reducing the width of high current transistors during the test
Keywords
CMOS analogue integrated circuits; analogue multipliers; design for testability; fault simulation; integrated circuit testing; operational amplifiers; power supply circuits; AC RMS supply current test; CMOS analogue multiplier circuit; DFT technique; DFTT scheme; HSPICE; analogue supply current tests; fault coverage; fault simulation; high current transistors; operational amplifier; Attenuators; CMOS analog integrated circuits; Circuit faults; Circuit testing; Current supplies; Design for testability; Electrical fault detection; Electronic equipment testing; Fault detection; Monitoring;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location
Lisboa
Print_ISBN
0-7803-5008-1
Type
conf
DOI
10.1109/ICECS.1998.814867
Filename
814867
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