On the multiple shared memory module approach to ATM switching

The authors propose a new approach to building large asynchronous transfer mode (ATM) switches based on shared memory modules. Shared memory modules are proposed to be placed in parallel, with every input and output port having access to every one of the switch models. This approach permits global sharing of the total buffer space. Some basic issues in such an arrangement are studied, such as the necessary and sufficient conditions for optimal performance and the minimum number of modules required for the switch to have optimal performance while permitting sharing of the entire buffer space among all the input and output ports and while preserving packet sequencing for any virtual channel. A centralized control algorithm which yields optimal performance is also proposed