A low-power memristive neuromorphic circuit utilizing a global/local training mechanism

As conventional CMOS technology approaches fundamental scaling limits novel nanotechnologies offer great promise for VLSI integration at nanometer scales. The memristor, or memory resistor, is a novel nanoelectronic device that holds great promise for continued scaling for emerging applications. Memristor behavior is very similar to that of the synapses necessary for realizing a neural network. In this research, we have considered circuits that leverage memristance in the realization of an artificial synapse that can be used to implement neuromorphic computing hardware. A charge sharing based neural network is described which consists of a hybrid of conventional CMOS technology and novel memristors. Results demonstrate that the circuit can be implemented with energy consumption on the order of tens of femto-joules. Furthermore, a training circuit is presented for implementing supervised learning in hardware with low area overhead.