Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology

Author

de Streel, Guerric ; Bol, David

Author_Institution

ICTEAM Inst., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium

fYear

2013

fDate

4-6 Sept. 2013

Firstpage

255

Lastpage

260

Abstract

Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of Back Biasing (BB) schemes on these features for FDSOI technology. We show that Forward BB can help cover a wider design space in term of optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on Minimum Energy Point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP.

Keywords

CMOS integrated circuits; integrated circuit design; low-power electronics; silicon-on-insulator; CMOS FDSOI; MEP; NMOS; PMOS; UTBB FDSOI technology; asymmetric back biasing; design space; forward back biasing scheme; minimum energy point; size 28 nm; subthreshold logic; ultra-low voltage logic; Delays; Leakage currents; Logic gates; MOS devices; Noise; Robustness; Systematics; 28nm; CMOS FDSOI; back gate biasing; die yield; robustness; subthreshold logic; ultra-low power; ultra-low-voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on

Conference_Location

Beijing

Print_ISBN

978-1-4799-1234-6

Type

conf

DOI

10.1109/ISLPED.2013.6629305

Filename

6629305