Energy evaluation methodology for platform based system-on-chip design

This paper presents a methodology that speeds up the process of estimating the system level energy efficiency for synthesisable AMBA based SOC platforms that are scalable by means of integrating additional intellectual property (IP) hardware through the AMBA bus system. The methodology facilitates a modular approach where overall energy consumption is calculated based on power models that are developed for each defined sub-block (or entity) of the platform. To automate the evaluation process we developed a tool - called PEX - that combines power models with utilisation statistics of the system entities, and that provides a fast way of analysing tradeoffs for speed, energy and power consumption for various system configurations. Detailed results are presented for the analysis of two implementation scenarios of the Rijndael AES algorithm using the SPARC V8 compatible LEON architecture.