Title :
Minimum area cost for a 30 to 70 Gbits/s AES processor
Author :
Hodjat, Alireza ; Verbauwhede, Ingrid
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
This paper presents the design decisions and area optimizations to obtain a high throughput, over 30 Gbits/s AES processor. With loop unrolling and outer-round pipelining techniques, throughputs of 30 Gbits/s to 70 Gbits/s are achievable in a 0.18 μm CMOS technology. Moreover, by using inner round pipelining of the composite field implementation of the substitution phase and designing an offline key scheduling unit for the AES processor the area cost is reduced by 48% while the same throughput is maintained. Therefore, the over 30 Gbits/s, fully pipelined AES processor operating in the counter mode can be use for the encryption of data on optical links.
Keywords :
CMOS integrated circuits; cryptography; microprocessor chips; optimisation; pipeline processing; processor scheduling; 0.18 microns; 30 to 70 Gbit/s; CMOS technology; area optimizations; composite field implementation; counter mode operation; data encryption; design decisions; fully pipelined AES processor; high throughput AES processor; inner round pipelining; loop unrolling; minimum area cost; offline key scheduling unit; optical links; outer-round pipelining techniques; Algorithm design and analysis; CMOS technology; Costs; Counting circuits; Cryptography; Data security; Optical fiber communication; Pipeline processing; Processor scheduling; Throughput;
Conference_Titel :
VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
Print_ISBN :
0-7695-2097-9
DOI :
10.1109/ISVLSI.2004.1339512
