DocumentCode
3498013
Title
Page policy control with memory partitioning for DRAM performance and power efficiency
Author
Mingli Xie ; Dong Tong ; Yi Feng ; Kan Huang ; Xu Cheng
Author_Institution
Microprocessor R&D Center, Peking Univ., Beijing, China
fYear
2013
fDate
4-6 Sept. 2013
Firstpage
298
Lastpage
303
Abstract
DRAM performance and power efficiency considerations are becoming increasingly important. Bank partitioning partitions memory banks among cores and eliminates inter-thread interference, thus improving system performance of shared memory CMP systems. However, it doesn´t take into account DRAM power consumption. We propose an application-aware page policy, which exploits potential benefits of page policy to optimize DRAM performance or minimize power consumption. The key idea is to dynamically assign page policy to applications according to their memory characteristics. As an improvement, we propose a power-aware bank partitioning to balance DRAM performance and power consumption. Experimental results show that our proposal increases system performance and significantly improves DRAM power efficiency.
Keywords
DRAM chips; paged storage; performance evaluation; power aware computing; shared memory systems; DRAM performance optimization; DRAM power consumption minimization; DRAM power efficiency; application-aware page policy control; memory bank partitioning; memory characteristics; power-aware bank partitioning; shared memory CMP systems; system performance; Interference; Memory management; Power demand; Proposals; Random access memory; System performance; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on
Conference_Location
Beijing
Print_ISBN
978-1-4799-1234-6
Type
conf
DOI
10.1109/ISLPED.2013.6629312
Filename
6629312
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